On-Chip Nanoscale Capacitor Decoupling Architectures for Hardware Security

On-chip decoupling capacitor optimization using architectural level prediction

Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular technique to counter this issue involves the usage of decoupling capacitors. This paper presents a novel design technique for sizing and placing on-chip decoupling capacitors based on activity signatures from the microarchit...

Hardware Architectures for Software Security

Deconstructing Hardware Architectures for Security

Researchers have recently proposed novel hardware architectures for enhancing system security. The proposed architectures address security threats such as buffer overflows, format string bugs, and information disclosure. The main advantage of hardware support is increased visibility into system state, low overheads for security checks, and, in some cases, compatibility with legacy binaries. Nev...

Reliability and Performance Evaluation of Fault-aware Routing Methods for Network-on-Chip Architectures (RESEARCH NOTE)

Nowadays, faults and failures are increasing especially in complex systems such as Network-on-Chip (NoC) based Systems-on-a-Chip due to the increasing susceptibility and decreasing feature sizes. On the other hand, fault-tolerant routing algorithms have an evident effect on tolerating permanent faults and improving the reliability of a Network-on-Chip based system. This paper presents reliabili...

Effective Decoupling Radius of Decoupling Capacitor*

Decoupling capacitors on packages and printed circuits boards are often essential to reduce voltage fluctuations and maintain power and signal integrity. This paper presents a measure for the evaluation of effectiveness of decoupling capacitors placed on package or board structures.